With the evolution of technology, the system complexity increased and the application fields of the embedded system expanded.\r\nCurrent applications need a high degree of performance, flexibility, and efficient development environments. Today, reconfigurable\r\nlogic allows to meet the on-chip processing requirements with new benefits resulting from partial and dynamic reconfiguration.\r\nBut the dimension introduced in the design of these systems requires more abstraction to manage their complexity and efficient\r\nmodels to provide reliable preliminary estimations. While classical multiprocessor systems can be modeled without difficulty, the\r\nuse of partial run-time reconfiguration in heterogeneous flexible system-on-chips is generally not covered. The contribution of\r\nthis paper is to address this with an extension of the AADL language able to model the reconfigurable logic, possibly considering\r\ndynamic reconfiguration and power consumption requirements. The proposed AADL model is divided into three levels to provide\r\na generic and hierarchical approach separating the static and dynamic parts of current FPGAs. These levels are exposed in detail\r\nand illustrated on a concrete example of FPGA device. The design space exploration of an application deployment using this model\r\nis also presented.
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